Vivek Singh
EEGR 491
Digital Signal Processing
Dr. Raymond Sova, Dr. Craig Scott
Department of Electrical Engineering, Morgan State University, Baltimore, MD
28 July 2011
Abstract
A low cost lockin amplifier has been designed and tested in order to measure the life time of common fluorophore for BioMedical Application. The Digital lock amplifier utilizes the SOPC builder for the desired user output. The design parameters were considered such that the frequency of weak signal was ensured while testing. The phase shift of the detected weak signal due to the delay was measured. This technique is precise and could be useful on various applications such as measuring the blood sugar level in blood, identifying the chemical composition of a compound and many more.
1. Introduction
The fluorescence lifetime measurement is one of the simple measurement techniques and it has now been widely used in biological, chemical, and physical sciences. It is because of its small low emission detection as the fluorescent samples have the characteristic behavior between emission and excitation. This would result in simple exponential decay function for many fluorophores, which could be used to determine its lifetime.
There are two ways of measuring the lifetime, one is the frequency domain method and other is the time domain method. The frequency domain was preferred for this research, since the fluorescence sample is excited by a modulated source of light which has a similar waveform as of the fluorescence emitted by the fluorohpore. Hence, there is a phase shift between the emitted fluorescence and the modulated source of light. The frequency domain method detects this phase shift of the fluorescent emission when the excitation light is modulated at 10 Megahertz. By observing the phase shift and modulation depth the fluorescent lifetime can be measured.
Signal amplification was done by a lock in amplifier. Lock in Amplifier is a device that provides a DC output proportional to the AC signal. It detects the very low signal of a particular frequency rejecting all other frequencies from a noisy environment. However, the physical device is very costly. Hence, the device was built digitally on an Altera Cyclone DE2 FPGA board to significantly reduce the cost and space required to operate the lock‐in amplifier. Another alternative would have been to design and build the amplifier with the easily available microchips on a breadboard, which is also expensive as compared to the FPGA design.
This device is very useful in detecting very small signals in presence of large background noise and to measuring the phase shift of large signals with high signal to noise ratio. Initially, the signal is multiplied by a reference function, mixing through a frequency mixer and the result is filtered using a low‐pass filter. For a signal Y (t) containing two frequencies when multiplied by the reference function R (t) the result is obtained X (t) is as follows:
Based on the frequency domain method a simple and cost efficient lifetime measurement system was designed using LED, a photomultiplier tube (PMT) and an oscilloscope system connected to a FPGA based lock‐in amplifier. The excitation and emission intensity for the fluorophore Alexa Fluor 647 with wave length of 647nm (red) was recorded and the raw data was manipulated using the custom algorithm in MATLAB software
2. High Level Design
The main technical objective of this research is to build all digital cost efficient lock-in amplifiers using FPGA board which could be used to perform the measurements as requires on the next part of the project. It would be performed using the steps shown on Fig 1. Each of the physical components used on signal processing would be designed individually as VHDL modules. A simple block diagram of a lock-in amplifier is shown on fig .
The other task would be to design a C programming module for the user interface. Due to the long debugging time the vga interface for the user was not used however, some of the modules were built and left it on the main verilog module for the future preferences.
The raw data acquired from the oscilloscope (data for calculation for this research was obtained fromwww.kps.or.kr) was saved and loaded into MATLAB and secondly data were processed using FFT and the phase of each individual wave was calculated using “angle” function on MATLAB.
The high level design for the lock-in amplifier is shown in fig.3. This design was made for the Altera Cyclone II DE2 board from Terasic. The snapshot of the board is shown in fig 2. The major advantage of DE2 board was it supports the hardware components needed, such as the basic FPGA support circuitry (power supply, programming, etc), as well switches and buttons for user input along with a VGA output port. However, for the purpose of lock-in the only disadvantage was that there is the absence of high speed A/D converters. However, the P0003_GPIO high speed digital acquisition was used to collect the data, which contains two ports of 100MS/s 14 bit DAC outputs and 2 port of 65MS/s 14 bit A/D input which was sufficient for a design goal of 1MHz input bandwidth.
For the purpose of the design, the input signal is first fed into the A/D which is then multiplied in a multiplier and passed though the low pass filter. It is then processed by NIOS II processor and sends the signal to output port A. Similarly, the reference signal is passed thought the A/D to the PLL (Phase Locked Loop), which is then mixed into the mixer and passed thorough the low pass filter. It is then processed by NIOS II processor into the output port B. 3. Verilog HDL Design
In order to build the system using the SOPC builder on Quartus II software all the verilog modules had to be separately constructed and compiled together. The top level verilog module was the main amplifier lockin_amp.v which defined all other supporting six verilog modules. The supporting verilog modules are character_generator.v, DDS_signal_generator.v, zero_crossing_detector.v, ntsc_display_generator.v, ref_digital_PLL.v, and exponential_decay_filter.v. These modules are discussed below:
Zero crossing detectors: This module simply took the digitized reference input, and waited for zero crossing. For the prevention of noise on the signal receptively triggering the crossing detects both positive and negative hysteresis was added. To prevent any phase shift the output was always triggered at the zero crossing.
ADPLL: Phase locked loop (PLL) was needed for an externally generated reference signal. Since, the goal was to digitized all the components, it was implemented as an all digital phase locked loop(ADPLL) such as input took a digitized data stream of the reference signal and as output gave a pair of locked quadrature sine waves. It was constructed using the QuartusII’s MegaWizard Plug in Manager.
Low Pass Filter: Low pass filters was designed to emulate the simple RC circuit with adjustable time constant. The quadrature mixers were implemented by a simple single pole IIR filter. It was done using two multipliers to multiply the two filter parameters against the input and previous output signal, respectively. The outputs were then summed, and stored in an output register which also previous output to the filter.
Exponential decay: This module was implemented using the equation for the output multiplier as, multiply_out = b1 * signal_out_old + a0 * signal_in
Each individual verilog module was created to function it as the physical digital component that would be programmed into the DE2 board.
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